The present invention relates to a mapping of a packet processing function onto a hybrid programmable logic device containing many programmable processors, dedicated function blocks, and programmable FPGA fabric.
A packet processor may accept ingress packets from a physical interface, perform classification and filtering operations on the packet, and then forward the packet to a traffic manager. The traffic manager interfaces with a switch fabric to switch packets onto egress packet processors and physical interfaces. Although there is no well-defined “packet processing” function, packet processing may include, but is not limited to, MAC capture and framing of packets, packet parsing, classification of packets into flows, maintenance of routing statistics and counters, IP translation, IP table lookup, or packet encapsulation and decapsulation. End applications of a packet processor may target one or more of the OSI transport layer, network layer, or application layer of the protocol stack.